Micron to work with JEDEC on 3D chip-stacking standard

12/18/2011 | XBitLabs.com

Micron Technology is coordinating efforts with JEDEC on developing an industry standard for three-dimensional stacking of DRAMs and interfaces. The 3DS technology may be incorporated into the DDR4 DRAM standard. In an effort to improve bus speed, signal integrity and timing while reducing power consumption, the 3D stacking technology involves master-and-slave DRAM die, with the master DRAM interfacing with the external memory controller.

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