Semiconductor manufacturers are turbocharging their transition to 96-layer 3D NAND flash process technology, seeking to improve yield rates as the tech barrels along to the chipmaking mainstream next year, industry sources say. The industry output with 96-layer 3D NAND is expected to overtake the 64-layer output in 2020, those sources note.
The emerging priorities of artificial intelligence and big data analytics are driving significant changes in memory technology, this analysis notes. Steven Woo of Rambus says, "The energy efficiency of AI systems is extremely important, so you want to arrange your models and training data in a way that you can retrieve large amounts of data each time you need to go to memory -- in effect, amortizing the high energy required to open and close the vault door."
Toshiba Memory wants to reduce its reliance on smartphones and consumer electronics, targeting the more profitable area in flash-based solid-state drives for data centers and ready to make merger-and-acquisition deals toward that goal. "One of the critical areas where we are focused on is the cloud service providers, data center players," Toshiba Memory Chairman Stacy Smith says.
Infineon Technologies turns to advanced neutral-point-clamped inverter design for the EasyPACK 2B hybrid power module, incorporating silicon carbide and insulated-gate bipolar transistor technology. The module is said to have increased power density and a switching frequency running up to 48 kilohertz.
Cadence Design Systems brought out Conformal Litmus, combining clock domain crossing signoff with constraints signoff for IC designs. The product is said to enhance the quality of silicon in complex system-on-a-chip designs, while reducing design cycle times.
CEOs of Xilinx, Arm and Micron Technology had differing takes on the status of Moore's Law during a Churchill Club discussion in San Jose, Calif. What they agreed upon is that the future of semiconductor technology remains bright, despite the technological challenges ahead.
Seven industry experts talk about IC design partitioning and its implications for microchip architectures in this roundtable interview. Raymond Nijssen of Achronix Semiconductor says, "One of the difficulties of individual partitions is that their behavior is becoming more dynamic these days."
Taiwan's suppliers of metal-oxide-semiconductor field-effect transistors are experiencing an uptick in orders from manufacturers of notebook computers and PCs, industry sources say. EST Technology Integration, Sinopower Semiconductor and Niko Semiconductor are among the MOSFET vendors seeing greater order visibility in the second half of 2019, those sources note.
Intel and SAP signed a multi-year agreement that will see the chipmaker's Xeon Scalable processors and Intel Optane DC persistent memory used to optimize SAP's software portfolio. "The goal here is [to expose] a broad portfolio of Intel technologies for the data-centric era, close collaboration with SAP to accelerate the pace of innovation of SAP's entire broad suite of enterprise-class applications, while making it easier for customers to see, test and deploy this technology," Intel's Rajeeb Hazra says.
A moire superlattice of trilayer graphene and hexagonal boron nitride could offer signatures of high-temperature superconductivity, according to researchers of the Lawrence Berkeley National Laboratory and the University of California at Berkeley. The team created their heterostructures by sandwiching exfoliated ABC-TLG and hBN with a dry transfer method.
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